Multi-channel, low nonlinearity time-to-digital converters based on 20nm and 28nm FPGAs

Chen, Haochang and Li, David Day-Uei (2018) Multi-channel, low nonlinearity time-to-digital converters based on 20nm and 28nm FPGAs. IEEE Transactions on Industrial Electronics. ISSN 0278-0046 (https://doi.org/10.1109/TIE.2018.2842787)

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Abstract

Abstract—This paper presents low nonlinearity, compact and multi-channel time-to-digital converters (TDC) in Xilinx 28nm Virtex 7 and 20nm UltraScale FPGAs. The proposed TDCs integrate several innovative methods that we have developed: 1) the sub-tapped delay line (TDL) averaging topology, 2) tap timing tests, 3) a direct compensation architecture and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25 % of the logic resources. The achieved least significant bit (LSB) is 10.5ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.

ORCID iDs

Chen, Haochang ORCID logoORCID: https://orcid.org/0000-0001-6196-4418 and Li, David Day-Uei ORCID logoORCID: https://orcid.org/0000-0002-6401-4263;
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