A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor

Kiat, Wei Pau and Mok, Kai Ming and Lee, Wai Kong and Goh, Hock Guan and Andonovic, Ivan; (2017) A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor. In: Proceedings - 31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017. IEEE, TWN, pp. 154-159. ISBN 9781509062300 (https://doi.org/10.1109/WAINA.2017.20)

[thumbnail of Kiat-etal-IEEE-WAINA-2017-A-comprehensive-analysis-on-data-hazard-for-RISC32-5-Stage]
Preview
 Text. Filename: Kiat_etal_IEEE_WAINA_2017_A_comprehensive_analysis_on_data_hazard_for_RISC32_5_Stage.pdf
Accepted Author Manuscript
Download (1MB)| Preview

Abstract

This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Instruction Set Architecture) compatible 5-stage pipeline processor, RISC32. Our work can be used as a reference for RISC32 processor developers to identify and resolve every possible data hazard that might arise during execution phase within the range of the basic MIPS core instruction set. The techniques used to resolve data hazard in this paper are data forwarding and pipeline stages stalling. When data hazard arises, it is first resolve by using data forwarding. If the problem persists, we use pipeline stages stalling then only follow by another data forwarding to resolve the data hazard. This combination will reduce the impact of data hazard on the processor throughput, instead of only using the pipeline stages stalling. This paper delivers a comprehensive analysis and the development of the data hazard resolving blocks that are able to resolve data hazard arises.

CORE (COnnecting REpositories)