Bit error rate performance evaluation of a silicon-on-insulator optical-network-on-chip router in a WDM configuration

Parini, Alberto and Bellanca, Gaetano and Annoni, Andrea and Morichetti, Francesco and Melloni, Andrea and Strain, Michael John and Sorel, Marc and Pareige, Christelle and Gay, Mathilde and Bramerie, Laurent and Thual, Monique; (2013) Bit error rate performance evaluation of a silicon-on-insulator optical-network-on-chip router in a WDM configuration. In: 39th European Conference and Exhibition on Optical Communication (ECOC 2013). IET, pp. 897-899. ISBN 9781849197595 (https://doi.org/10.1049/cp.2013.1572)

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Abstract

We present a microring-based integrated router in Silicon-on-Insulator technology suitable for optical networking at chip level. The switching functionalities in a 3-channels 10 Gbit/s WDM configuration are evaluated through the BER curves. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.

ORCID iDs

Parini, Alberto, Bellanca, Gaetano, Annoni, Andrea, Morichetti, Francesco, Melloni, Andrea, Strain, Michael John ORCID logoORCID: https://orcid.org/0000-0002-9752-3144, Sorel, Marc, Pareige, Christelle, Gay, Mathilde, Bramerie, Laurent and Thual, Monique;
CORE (COnnecting REpositories)