Hardware co-simulation in system generator of the AES-128 encryption algorithm

Tools

Denning, D.J. and Devlin, M. and Irvine, J. (2004) Hardware co-simulation in system generator of the AES-128 encryption algorithm. In: ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004-02-22 - 2004-02-23. (https://doi.org/10.1145/968280.968322)

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Abstract

We discuss the use of System Generator to hardware co-simulate in the FPGA versions of the AES-128 encryption algorithm. We show that the FPGA co-simulation of the AES can be achieved over 3 different bus types (TCP/IP, board-level TCP/IP, and PCI). One of the FPGA co-simulations is over 3 times faster running over a TCP/IP network distance off approximately 600 kilometres, than running a normal Simulink simulation on the host PC. Another hardware co-simulation time increases in the region of 4000% running over the PCI bus attached to the host PC. By having this FPGA co-simulation option, some of the IP cores in an FPGA system can be co-simulated, there by freeing up processing power on the host-PC for further developments in a system.

ORCID iDs

Denning, D.J., Devlin, M. and Irvine, J. ORCID logoORCID: https://orcid.org/0000-0003-2078-6517;
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