Via hole addressed TFT and process for large-area a-Si:H electronics

Gleskova, Helena and Wagner, S. and Shen, D.; Wagner, S. and Hack, M. and Schiff, E. A. and Schropp, R. and Shimizu, I., eds. (1997) Via hole addressed TFT and process for large-area a-Si:H electronics. In: Amorphous and Microcrystalline Silicon Technology - 1997. MRS Symposium Proceedings, 467 . Materials Research Society, USA, pp. 869-874. ISBN 1558993711

Abstract

We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. AU gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 mu m in 50 mu m glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.

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• Item metadata

  Item type:	Book Section
  ID code:	33503
  Dates:	Date Event 1997 Published
  Subjects:	Technology > Electrical engineering. Electronics Nuclear engineering
  Department:	Faculty of Engineering > Electronic and Electrical Engineering
  Depositing user:	Pure Administrator
  Date deposited:	27 Sep 2011 15:23
  Last modified:	08 Apr 2024 12:48
  URI:	https://strathprints.strath.ac.uk/id/eprint/33503