Investigation of the impact of interoperability of voltage source converters on HVDC grid fault behaviour
Psaras, Vasileios and Emhemed, Abdullah and Adam, Grain Philip and Burt, Graeme (2019) Investigation of the impact of interoperability of voltage source converters on HVDC grid fault behaviour. In: The 15th IET International Conference on AC and DC Power Transmission (ACDC 2019), 2019-02-05 - 2019-02-07, DoubleTree by Hilton Hotel Coventry.
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Abstract
Future HVDC grids are expected to incorporate different power converters from multiple vendors in the same system. Even if a complete converter station is developed by a single manufacturer, it might be challenging to integrate this terminal into a DC grid that comprises of several converter stations built by other vendors. Moreover, the different fault response exhibited by each converter technology complicates the design of HVDC protection systems. Therefore, this study investigates the fault response of a multivendor HVDC grid. An illustrative 4-terminal meshed HVDC grid, which is modelled in PSCAD environment, is used to perform studies of interoperability of different converter topologies on a common HVDC network. The investigation of the fault behaviour of such a multivendor HVDC network highlights the main impediments that need to be tackled and a set of actions that needs to be done at a converter level in order to mitigate the impact of DC faults on the HVDC system. Moreover, the key parameters that need to be taken into account when designing a protection scheme for a multivendor HVDC grid are identified.
ORCID iDs
Psaras, Vasileios, Emhemed, Abdullah ORCID: https://orcid.org/0000-0002-4635-0167, Adam, Grain Philip ORCID: https://orcid.org/0000-0002-1263-9771 and Burt, Graeme ORCID: https://orcid.org/0000-0002-0315-5919;-
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Item type: Conference or Workshop Item(Paper) ID code: 67163 Dates: DateEvent7 February 2019Published23 October 2018Accepted16 May 2018SubmittedSubjects: Technology > Electrical engineering. Electronics Nuclear engineering Department: Faculty of Engineering > Electronic and Electrical Engineering Depositing user: Pure Administrator Date deposited: 06 Mar 2019 10:09 Last modified: 11 Nov 2024 16:54 URI: https://strathprints.strath.ac.uk/id/eprint/67163