Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance

Liu, Dawei and Hollis, Simon J. and Dymond, Harry C. P. and McNeill, Neville and Stark, Bernard H. (2016) Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance. IEEE Transactions on Circuits and Systems II: Express Briefs, 63 (7). pp. 688-692. ISSN 1558-3791

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    Abstract

    A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.