A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations

Chen, Haochang and Zhang, Yongliang and Li, David Day-Uei (2017) A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations. IEEE Transactions on Instrumentation and Measurement, 66 (7). 1912 - 1921. ISSN 0018-9456

[img]
Preview
 Text (Chen-etal-TIM-2016-A-low-nonlinearity-missing-code-free-time-to-digital)
Chen_etal_TIM_2016_A_low_nonlinearity_missing_code_free_time_to_digital.pdf
Final Published Version
License: Creative Commons Attribution 3.0 logo
Download (2MB)| Preview

    Abstract

    This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28nm Field Programmable Gate Array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the non-uniformity originated from carry chains, and use a multi-phase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [-0.38, 0.87] LSB (the least significant bit: 10.5 ps) with σDNL = 0.20 LSB, and the integral nonlinearity (INL) is within [-1.23, 1.02] LSB with σ INL = 0.50 LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNLpk-pk (peak-to-peak DNL) and INLpk-pk (peak-to-peak INL) can be reduced to 0.08LSB with σDNL = 0.01LSB and 0.13 LSB with σINL = 0.02LSB respectively.

    Creators(s): Chen, Haochang ORCID logoORCID: https://orcid.org/0000-0001-6196-4418, Zhang, Yongliang and Li, David Day-Uei ORCID logoORCID: https://orcid.org/0000-0002-6401-4263;
    Item type:Article
    ID code:60425
    Notes:© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
    Keywords:bin width, carry chains, field-programmable gate arrays, multi-phase clock, time-of-flight, time-to-digital converters, Virtex-7, Electrical engineering. Electronics Nuclear engineering, Electrical and Electronic Engineering
    Subjects:Technology > Electrical engineering. Electronics Nuclear engineering
    Department:Faculty of Science > Strathclyde Institute of Pharmacy and Biomedical Sciences
    Strategic Research Themes > Health and Wellbeing
    Depositing user: Pure Administrator
    Date deposited:11 Apr 2017 10:39
    Last modified:29 Mar 2020 02:02
    Related URLs:
    URI:https://strathprints.strath.ac.uk/id/eprint/60425
    Export data:
    CORE (COnnecting REpositories)