DC fault parameter sensitivity analysis

Page, Frederick and Adam, Grain and Finney, Stephen and Holliday, Derrick and Xu, Lie; (2014) DC fault parameter sensitivity analysis. In: Proceedings of the 12th IET International Conference on Developments in Power System Protection (DPSP 2014). Institution of Engineering and Technology, GBR. ISBN 9781849198349 (https://doi.org/10.1049/cp.2014.0014)

[thumbnail of Page_etal_DPSP_2014_DC_fault_parameter_sensitivity_analysis]
Preview
 Text. Filename: Page_etal_DPSP_2014_DC_fault_parameter_sensitivity_analysis.pdf
Accepted Author Manuscript
Download (785kB)| Preview

Abstract

At present High Voltage Direct Current (HVDC) Voltage Source Converters (VSC) are susceptible dc faults leading to extreme currents. The fault current cannot be controlled by the converter switching flows in the anti-parallel diodes. Protection devices are, therefore, required to operate with sufficient speed to avoid device failure. A method is introduced to calculate the critical time for protection to operate. Using this method it is then shown how the critical time may be extended by way of optimization of passive system components. In order to perform this optimization a new post-fault (when the converter gating signals are inhibited) model of the Modular Multi-Level (MMC) converter is introduced which drastically reduces simulation time, allowing high resolution parameter sweeps to be performed. The model is validated and is shown to produce fault characteristics similar to that of a conventional switched model.

ORCID iDs

Page, Frederick ORCID logoORCID: https://orcid.org/0000-0001-9757-2889, Adam, Grain ORCID logoORCID: https://orcid.org/0000-0002-1263-9771, Finney, Stephen ORCID logoORCID: https://orcid.org/0000-0001-5039-3533, Holliday, Derrick ORCID logoORCID: https://orcid.org/0000-0002-6561-4535 and Xu, Lie ORCID logoORCID: https://orcid.org/0000-0001-5633-7866;
CORE (COnnecting REpositories)