Via hole addressed TFT and process for large-area a-Si:H electronics

Gleskova, Helena and Wagner, S. and Shen, D.; Wagner, S. and Hack, M. and Schiff, E. A. and Schropp, R. and Shimizu, I., eds. (1997) Via hole addressed TFT and process for large-area a-Si:H electronics. In: Amorphous and Microcrystalline Silicon Technology - 1997. MRS Symposium Proceedings, 467 . Materials Research Society, USA, pp. 869-874. ISBN 1558993711

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Abstract

We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. AU gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 mu m in 50 mu m glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.

ORCID iDs

Gleskova, Helena ORCID logoORCID: https://orcid.org/0000-0001-7195-9639, Wagner, S. and Shen, D.; Wagner, S., Hack, M., Schiff, E. A., Schropp, R. and Shimizu, I.
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