Via hole technology for thin-film transistor circuits
Gleskova, H. and Wagner, S. and Zhang, Q. and Shen, D. S. (1997) Via hole technology for thin-film transistor circuits. IEEE Electron Device Letters, 18 (11). pp. 523-525. ISSN 0741-3106 (https://doi.org/10.1109/55.641433)
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We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.
ORCID iDs
Gleskova, H.
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Item type: Article ID code: 33413 Dates: DateEvent1997PublishedKeywords: hole technology, film transistor circuits, thin-film transistor, Electrical Engineering. Electronics Nuclear Engineering, Electronic, Optical and Magnetic Materials, Electrical and Electronic Engineering Subjects: Technology > Electrical engineering. Electronics Nuclear engineering Department: Faculty of Engineering > Electronic and Electrical Engineering Depositing user: Pure Administrator Date deposited: 12 Oct 2011 14:58 Last modified: 01 Nov 2023 09:47 Related URLs: URI: https://strathprints.strath.ac.uk/id/eprint/33413
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