Via hole technology for thin-film transistor circuits

Gleskova, H. and Wagner, S. and Zhang, Q. and Shen, D. S. (1997) Via hole technology for thin-film transistor circuits. IEEE Electron Device Letters, 18 (11). pp. 523-525. ISSN 0741-3106 (https://doi.org/10.1109/55.641433)

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Abstract

We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.

ORCID iDs

Gleskova, H. ORCID logoORCID: https://orcid.org/0000-0001-7195-9639, Wagner, S., Zhang, Q. and Shen, D. S.;
CORE (COnnecting REpositories)