Rapid prototyping of a test harness for forward error correcting codes

Tools

Irvine, James and Brown, E. and Wilkie, W. (2005) Rapid prototyping of a test harness for forward error correcting codes. In: FPGA '05 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 2005-02-20 - 2005-02-22. (https://doi.org/10.1145/1046192.1046258)

Full text not available in this repository.Request a copy

Abstract

This paper presents a design flow for the rapid prototyping of forward error correction (FEC) systems in the Xilinx System Generator tool. In this instance two FEC systems were tested, both Turbo codec's. One was designed to comply with the UMTS standard, the other was designed to comply with the cdma2000 standard. The target hardware for this system is a Field Programmable Gate Array (FPGA). The System Generator tool and the cdma2000 Turbo code standard are discussed. A description of the implemented test harness is given along with simulation results and a comparison of simulation times for both hardware and software implementations of the system.

ORCID iDs

Irvine, James ORCID logoORCID: https://orcid.org/0000-0003-2078-6517, Brown, E. and Wilkie, W.;
CORE (COnnecting REpositories)