Interface compensation for more accurate power transfer and signal synchronization within power hardware-in-the-loop simulation

Feng, Zhiwang and Pena Alzola, Rafael and Seisopoulos, Paschalis and Syed, Mazheruddin Hussain and Guillo-Sansano, Efren and Norman, Patrick and Burt, Graeme; (2021) Interface compensation for more accurate power transfer and signal synchronization within power hardware-in-the-loop simulation. In: IECON 2021 – 47th Annual Conference of the IEEE Industrial Electronics Society. IECON Proceedings (Industrial Electronics Conference) . IEEE, CAN. ISBN 9781665435543

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    Abstract

    Power hardware-in-the-loop (PHIL) simulation leverages the real-time emulation of a large-scale complex power system, while also enabling the in-depth investigation of novel actual power components and their interactions with the emulated power grid. The dynamics and non-ideal characteristics (e.g., time delay, non-unity gain, and limited bandwidth) of the power interface result in stability and accuracy issues within the PHIL closed-loop simulations. In this paper, a compensation method is proposed to compensate for the non-ideal power interface by maximizing its bandwidth, maintaining its unity-gain characteristic, and compensating for its phase-shift over the frequencies of interest. The accuracy of power signals synchronization and the transparency of power transfer within the PHIL configuration are assessed by employing the error metrics. In conjunction with the frequency-domain stability analysis and the time-domain simulations, a case study is made to validate the proposed compensation method.

    ORCID iDs

    Feng, Zhiwang ORCID logoORCID: https://orcid.org/0000-0001-5612-0050, Pena Alzola, Rafael, Seisopoulos, Paschalis, Syed, Mazheruddin Hussain ORCID logoORCID: https://orcid.org/0000-0003-3147-0817, Guillo-Sansano, Efren, Norman, Patrick ORCID logoORCID: https://orcid.org/0000-0001-5577-1281 and Burt, Graeme ORCID logoORCID: https://orcid.org/0000-0002-0315-5919;