A scheme to improve the stability and accuracy of power hardware-in-the-loop simulation

Feng, Zhiwang and Peña Alzola, Rafael and Seisopoulos, Paschalis and Guillo Sansano, Efren and Syed, Mazheruddin Hussain and Norman, Patrick and Burt, Graeme; (2020) A scheme to improve the stability and accuracy of power hardware-in-the-loop simulation. In: IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society. IEEE, SGP, pp. 5027-5032. ISBN 978-1-7281-5414-5

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    Abstract

    Power hardware-in-the-loop (PHIL) is a state-of-the-art simulation technique that combines real-time digital simulation and hardware experiments into a closed-loop testing environment. The transportation delay or communication latency impacts the stability and accuracy of PHIL simulations. In this paper, for the purpose of synchronizing the PHIL output signal and promoting both the stability and accuracy of PHIL simulation, a hybrid compensation scheme is proposed to compensate for the time delay in the PHIL configuration. A model-based compensator is implemented to shift the time delay out of the PHIL closed-loop to enhance PHIL stability. A time delay compensation model and its equivalent inverse model are employed in the PHIL closed-loop to compensate for the time delay. A phase lead compensator and digital linear-phase frequency sampling filter (FSF) are candidate compensation models to compensate for the time delay and reshape the phase curve on a harmonic-by-harmonic basis. Simulations are made to validate the effectiveness of the compensation scheme.

    ORCID iDs

    Feng, Zhiwang ORCID logoORCID: https://orcid.org/0000-0001-5612-0050, Peña Alzola, Rafael, Seisopoulos, Paschalis, Guillo Sansano, Efren ORCID logoORCID: https://orcid.org/0000-0002-2773-4157, Syed, Mazheruddin Hussain ORCID logoORCID: https://orcid.org/0000-0003-3147-0817, Norman, Patrick ORCID logoORCID: https://orcid.org/0000-0001-5577-1281 and Burt, Graeme ORCID logoORCID: https://orcid.org/0000-0002-0315-5919;