Analysis of DC fault for dual active bridge DC/DC converter including prototype verification

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Rahman, M. I. and Ahmed, K.H. and Jovcic, D. (2018) Analysis of DC fault for dual active bridge DC/DC converter including prototype verification. IEEE Journal of Emerging and Selected Topics in Power Electronics. ISSN 2168-6777 (https://doi.org/10.1109/JESTPE.2018.2856759)

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Abstract

This paper presents DC fault analysis for a dual active bridge DC/DC converter which comprises of two active bridges and an internal medium frequency transformer. This topology provides galvanic isolation, voltage step up/ down and bidirectional power transfer. The DC fault study assumes the DC terminal voltage of the converter is at zero . T he steady state fault current is limited to a low magnitude which is less than the rated value without any control ler action depending o n the design of the converter . The DC faults current magnitudes are analyzed with AC equivalent circuit where only the fundamental component of the AC voltages and inductor current are considered . P hase shift and AC voltage magnitude modulation control met hods are selected . A detailed dual active bridge DC/DC converter 3 MW, 4/40 kV based system is simulated using MATLAB/Simulink to validate the proposed analytical study. Further, hardware testing is conducted to confirm the DC fault studies with a 500 W 24 /100 V prototype.

  • Item type:Article
    ID code:64662
    Dates:
    Date
    Event
    17 July 2018
    Published
    17 July 2018
    Published Online
    1 July 2018
    Accepted
    Notes:© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
    Subjects:Technology > Electrical engineering. Electronics Nuclear engineering
    Department:Faculty of Engineering > Electronic and Electrical Engineering
    Depositing user: Pure Administrator
    Date deposited:03 Jul 2018 11:24
    Last modified:11 Nov 2024 12:02
    Related URLs:
    URI:https://strathprints.strath.ac.uk/id/eprint/64662
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