Automatic FFT code generation for FPGA with high flexibility and human readability

Tools

O'Sullivan, John and Weiss, Stephan and Rice, Garrey; (2011) Automatic FFT code generation for FPGA with high flexibility and human readability. In: Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011. IEEE, USA, pp. 2197-2201. ISBN 978-1-4673-0321-7 (https://doi.org/10.1109/ACSSC.2011.6190421)

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Abstract

This paper describes a Fast Fourier Transform (FFT) core which uses code generation to create optimised Hardware Description Language (HDL) code for a radix-2, decimation in time FFT. The generated code is designed to be human readable, vendor non-specific and is available in both Verilog and VHDL languages. A choice of In-place or Multipath Delay Commutator (MDC) architectures is provided. Selectable architectures and generic, readable HDL code make the core highly flexible for use in different applications and with different hardware platforms. The implementation of the available architectures and their relative merits are discussed. Maximum clock speed and resource requirements are examined and compared.

ORCID iDs

O'Sullivan, John, Weiss, Stephan ORCID logoORCID: https://orcid.org/0000-0002-3486-7206 and Rice, Garrey;
CORE (COnnecting REpositories)