Compact iterative FPGA camellia algorithm implementations

Denning, D. and Irvine, J. and Devlin, M. (2004) Compact iterative FPGA camellia algorithm implementations. In: 3rd International Conference on Field-Programmable Technology, 2004-12-06 - 2004-12-08. (https://doi.org/10.1109/FPT.2004.1393287)

Abstract

In this paper we present various iterative Camellia encryption algorithm implementations. The algorithm uses a 128-bit key, which keeps the algorithm as small as possible. The purpose for this implementation is for low-cost or area-restricted implementations suitable for embedded or mobile applications. We discuss the design and implementation considerations for a feedback architecture and achieve a throughput of 426Mbits/sec without key scheduling and 388Mbit/sec with key scheduling.

ORCID iDs

Irvine, J. ORCID: https://orcid.org/0000-0003-2078-6517

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• Item metadata

  Item type:	Conference or Workshop Item(Paper)
  ID code:	39124
  Dates:	Date Event December 2004 Published
  Subjects:	Technology > Electrical engineering. Electronics Nuclear engineering
  Department:	Faculty of Engineering > Electronic and Electrical Engineering
  Depositing user:	Pure Administrator
  Date deposited:	12 Apr 2012 13:18
  Last modified:	11 Nov 2024 16:17
  URI:	https://strathprints.strath.ac.uk/id/eprint/39124