Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters

Gao, L. and Fletcher, J.E. and Reay, D. and Zheng, L. (2006) Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters. In: 3rd IET International Conference on Power Electronics, Machines and Drives, 2006-04-04 - 2006-04-06. (https://doi.org/10.1049/cp:20060135)

Abstract

The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.

• Share and Export
  

  RefWorksRIS (EndNote Online, Zotero, Ref manager, etc)RDF+XMLEndNoteASCII CitationOpenURL ContextObject in SpanMPEG-21 DIDLRIOXX2 XMLBibTeXAtomEP3 XMLDublin CoreRDF+N-TriplesMODSHTML CitationJSONData Cite XMLRDF+N3Multiline CSVOpenURL ContextObjectReferSimple MetadataMETS
• Item metadata

  Item type:	Conference or Workshop Item(Paper)
  ID code:	37613
  Dates:	Date Event 2006 Published
  Subjects:	Technology > Electrical engineering. Electronics Nuclear engineering
  Department:	Faculty of Engineering > Electronic and Electrical Engineering
  Depositing user:	Pure Administrator
  Date deposited:	13 Feb 2012 15:00
  Last modified:	11 Nov 2024 16:21
  URI:	https://strathprints.strath.ac.uk/id/eprint/37613