IP core for hardware RAID 6 acceleration

Gilroy, M.P. and Irvine, J. and Riddell, Gideon (2006) IP core for hardware RAID 6 acceleration. In: IP Based SOC Design Conference and Exhibition, 2006-12-06 - 2006-12-07.

Abstract

As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware

ORCID iDs

Irvine, J. ORCID: https://orcid.org/0000-0003-2078-6517

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• Item metadata

  Item type:	Conference or Workshop Item(Paper)
  ID code:	37373
  Dates:	Date Event 2006 Published
  Subjects:	Technology > Electrical engineering. Electronics Nuclear engineering
  Department:	Faculty of Engineering > Electronic and Electrical Engineering
  Depositing user:	Pure Administrator
  Date deposited:	03 Feb 2012 16:45
  Last modified:	11 Nov 2024 16:21
  Related URLs:	Journal or Publication
  URI:	https://strathprints.strath.ac.uk/id/eprint/37373