A design flow for partially reconfigurable hardware

Robinson, I. and Irvine, J. (2004) A design flow for partially reconfigurable hardware. ACM Transactions in Embedded Computing Systems, 3 (2). pp. 257-283. ISSN 1539-9087 (http://dx.doi.org/10.1145/993396.993399)

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Abstract

This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing), synthesis, automatic placement and routing, partial configuration generation and control of partially reconfigurable designs. Collectively these tools constitute the dynamic circuit switching CAD framework. A partially reconfigurable Viterbi decoder design is presented to demonstrate the design flow and illustrate possible power consumption reductions and performance improvements through the exploitation of partial reconfiguration.

ORCID iDs

Robinson, I. and Irvine, J. ORCID logoORCID: https://orcid.org/0000-0003-2078-6517;
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