Modeling of gate line delay in very large active matrix liquid crystal displays

Zhang, Q. and Shen, D. and Gleskova, Helena and Wagner, S. (1998) Modeling of gate line delay in very large active matrix liquid crystal displays. IEEE Transactions on Electron Devices, 45 (1). pp. 343-345. ISSN 0018-9383 (https://doi.org/10.1109/16.658856)

Full text not available in this repository.Request a copy

Abstract

With standard inverted-staggered amorphous silicon based TFT's, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten.

ORCID iDs

Zhang, Q., Shen, D., Gleskova, Helena ORCID logoORCID: https://orcid.org/0000-0001-7195-9639 and Wagner, S.;
  • Item type:Article
    ID code:33411
    Dates:
    Date
    Event
    1998
    Published
    Keywords:voltage, active matrix liquid crystal displays , amorphous silicon ,, conductors , delay effects , delay lines , joining processes , power transmission lines , Electrical engineering. Electronics Nuclear engineering, Electronic, Optical and Magnetic Materials, Electrical and Electronic Engineering
    Subjects:Technology > Electrical engineering. Electronics Nuclear engineering
    Department:Faculty of Engineering > Electronic and Electrical Engineering
    Depositing user: Pure Administrator
    Date deposited:12 Oct 2011 14:48
    Last modified:20 Jan 2021 19:33
    URI:https://strathprints.strath.ac.uk/id/eprint/33411
CORE (COnnecting REpositories)