Modeling of gate line delay in very large active matrix liquid crystal displays

Zhang, Q. and Shen, D. and Gleskova, Helena and Wagner, S. (1998) Modeling of gate line delay in very large active matrix liquid crystal displays. IEEE Transactions on Electron Devices, 45 (1). pp. 343-345. ISSN 0018-9383 (https://doi.org/10.1109/16.658856)

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Abstract

With standard inverted-staggered amorphous silicon based TFT's, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten.

ORCID iDs

Zhang, Q., Shen, D., Gleskova, Helena ORCID logoORCID: https://orcid.org/0000-0001-7195-9639 and Wagner, S.;
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