A stepped-spacer FinFET design for enhanced device performance in FPGA applications

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Zareiee, Meysam and Mehrad, Mahsa and Tawfik, Abdulkarim (2025) A stepped-spacer FinFET design for enhanced device performance in FPGA applications. Micromachines, 16 (8). 867. ISSN 2072-666X (https://doi.org/10.3390/mi16080867)

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Abstract

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S3-FinFET) that incorporates a three-layer HfO2/Si3N4/HfO2 spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S3-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S3-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments.

ORCID iDs

Zareiee, Meysam ORCID logoORCID: https://orcid.org/0000-0002-5637-1746, Mehrad, Mahsa and Tawfik, Abdulkarim;
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