Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH

Ramsay, Craig and Crockett, Louise H. and Stewart, Robert W.; Matthews, Michael B., ed. (2022) Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH. In: 55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021. Asilomar Conference on Signals, Systems, and Computers . IEEE, USA, pp. 925-932. ISBN 9781665458283 (https://doi.org/10.1109/IEEECONF53345.2021.9723107)

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Abstract

We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches in a novel hierarchy: efficient parallelism with Fast FIR Algorithm (FFA) structures, and efficient multiplierless FIR implementations with Hcub. The resource usage advantages (in both area and type) are compared with similar output from the traditional architecture, exemplified by vendor tools, as well as the Hcub-based filters without the FFA optimisation. Although these techniques are well studied individually in the literature, they have not enjoyed mainstream use as their structural complexity proves awkward to capture with traditional Hardware Description Languages (HDLs). This work continues a discussion of the use of functional programming techniques in hardware description, highlighting the benefits of having easily composable circuit generators.