New Efficient Submodule for a Modular Multilevel Converter in Multiterminal HVDC Networks

In high-voltage applications, the magnitude of total semiconductor losses (on-state and switching) determines the viability of modular-type multilevel converters. Therefore, this paper presents a new cell arrangement that aims to lower total semiconductor loss of the modular multilevel converter (MMC) to less than that of the half-bridge modular multilevel converter (HB-MMC). Additional attributes of the proposed cell are: it eliminates the protective thyristors used in conventional half-bridge cells that deviate part of the dc-fault current away from the antiparallel diode of the main switch when the converter is blocked during a dc short-circuit fault, and it can facilitate continued operation of the MMC during cell failures without the need for a mechanical bypass switch. Thus, the MMC that uses the proposed cell retains all advantages of the HB-MMC such as full modularity of the power circuit and internal fault management. The claimed attributes of the proposed cell are verified using illustrative simulations and reduced scale experimentations. Additionally, this paper provides brief and critical discussions that highlight the attributes and limitations of popular MMC control methods and different MMC cells structures proposed in the literature, considering the power electronic system perspective.

complex capacitor voltage balancing and suffer from high capacitor voltage ripple due to the lack of redundant switch states that can be used to balance the cell capacitor voltages at the cell level (each voltage level can be generated by only one state, and upper capacitor of the cell in Figure 1 (c) and (d) cannot be selected or inserted into the power path unless the lower capacitor is already inserted into power path).
Each asymmetric bipolar cell in Figure 1 (f) and (g) inserts three semiconductor switches in the conduction path per cell during normal operation, and can exploit the negative voltage level it generates to allow MMC upper and lower arm voltages to be varied between V dc0 and 0 during normal operation, and ½V dc0 and -½V dc0 during operation with zero dc link voltage, see Figure 2 (a) and (c). Such operation permits MMC cell capacitor voltages to be regulated independent of the dc link voltage (V dc ), and enables MMC upper and lower arms to generate bipolar voltages that can be used to counter the dc link voltage (V dc ) as it varies between 0 and V dc0 (including during dc short circuit fault). As a result, the MMCs that employ the asymmetrical cells in Figure 1 (f) and (g) are able to deal with dc faults better than those using unipolar cells, while retaining full control over the active and reactive power they exchange with the ac grid [4,5,13]. Among the asymmetrical bipolar cells, the hybrid cell in Figure 1   during normal operation with rated positive and negative dc link voltage, and between ½V dc0 and -½V dc0 during operation with 0 dc link voltage, see Figure 2 (a) and (d). Such operational flexibility allows MMCs that employ symmetrical bipolar cells to generate peak output phase voltage V m >½m max V dc0 (over-modulation), without reappearance of the low-order harmonics in the baseband as in traditional voltage source converters; where, m max represents the maximum modulation index. The aforesaid attributes allow MMCs that use symmetrical bipolar cells to have the largest control range (see Figure 2 (d)), tolerance to dc faults, and bipolar dc link voltage operation. But these attributes are achieved at the expense of increased semiconductor losses compared to their counterparts that employ unipolar and asymmetrical bipolar cells [5,13,14]. The authors in [15] proposed a new type of symmetrical bipolar cell that can generate seven voltage levels to be used in modular ac/ac and dc/ac converters. The modular converter that uses the proposed cell can generate more voltage levels per phase using reduced number of switching devices compared to full-bridge MMCs; thus, the proposed cell is expected to be attractive for applications that demand high quality output voltage and current waveforms. Additionally, the operating envelope of the MMC that uses the proposed cell is expected to be similar to that of the full-bridge MMC, including operation with positive and negative dc link voltage and dc fault reverse blocking. The proposed cell inserts two fewer IGBTs in the conduction path compared to the equivalent full-bridge cells; hence, its semiconductor losses is expected to be lower than the full-bridge cell. The main limitations of the proposed cell is lack of modularity as the rated voltage of the upper capacitor is three times that of the lower capacitor, and rated voltage of the middle switch devices is twice that of the upper and lower switches.
In recent years, several methods have emerged that can be used to control modular multilevel converters, with some methods offer maximum control range and flexibility [12,16,17]. Some of the popular methods to control half-bridge modular converter is the standard decoupled current controller in synchronous reference frame that rotates at fundamental frequency (ω), with a dedicated supplementary controller for suppression of the 2 nd order harmonic current in the phase variables or the synchronous reference frame at twice the fundamental frequency [7,13,[18][19][20]. In this control method, the controller that suppresses the 2 nd order harmonic current in each MMC phase leg injects the necessary harmonics into modulation functions of the upper and lower arms in order to suppress the parasitic component of the common-mode current (both ac and dc components of modulation functions are modified). Although this control approach is relatively slow and cell capacitor voltages are highly coupled to dc link voltage, its ability to suppress 2 nd order harmonic current in converter arms to virtually zero makes it well suited for HVDC applications, where converter semiconductor losses (on-state and switching) are paramount.
An improved version of the method discussed in [7,13,[18][19][20], which includes two additional cascaded control loops that regulate the average cell capacitor voltage per phase leg and common-mode current [21][22][23]. This control method could be used with MMCs that employ half or full-bridge cells and other symmetrical and asymmetrical bipolar cells in Figure 1 in order to decouple the control of cell capacitor voltages from the dc link voltage. In this manner, active and reactive powers could be controlled independent of the dc link voltage in asymmetrical and symmetrical bipolar cells, and over a limited range in unipolar cells such as the half-bridge cell. The main shortcoming of this control method when it is used with half-bridge and other unipolar cells is that the MMC arms experience relatively high currents during reduced dc link voltage operation, should the cell capacitor voltages to be controlled independent of the dc link voltage (fixed at nominal dc link voltage V dc0 ).
The authors in [24][25][26][27][28][29][30][31] presented several control methods for half and full-bridge modular converters that employ phase-shifted carriers pulse width modulation. The refined version of this control method is presented in [26], which includes a number of dedicated controllers for common-mode voltage per phase (average capacitor voltage per phase leg), upper and lower arm voltage balancing and individual cell capacitor voltage balancing (these controllers ensure vertical balancing); and controller that ensures the dc link current is evenly distributed between the phase leg (the average common-mode current in each phase leg must be equal to one third of the dc link current, and this controller is for ensuring horizontal balancing). Additionally, basic converter controllers such as dc link voltage and active and reactive powers could be included. The main attributes of this control approach are: fixed switching frequency per device, independent of operating condition (this makes thermal management and heatsink design simpler); and no need for time consuming capacitor voltage sorting (which is extremely useful should MMC adopted in dc transformers, with relatively high fundamental frequency). But increased reliance on the control system at the modulation level may raise concern regarding the reliability of this control method; especially, during operation in harsh power system environments.
Several methods for controlling MMCs using energy manipulation have been proposed in [16,[32][33][34]. For example, the method presented in [16] uses the zero sequence (dc) and negative sequence (2 nd order harmonic current) component of the common-mode current of each phase leg to regulate the total energy stored per converter to be constant and to suppress the cell capacitor energy fluctuations to virtually zero in an attempt to drastically reduce capacitor voltage ripple. Whilst the positive sequence of the common-mode current at fundamental frequency is used to ensure energy balance between the upper and lower arms of each phase leg. Although this approach is interesting, the choice of capacitor voltage ripple instead of the suppression of the 2 nd order harmonic currents in MMC arms is not appropriate for HVDC applications, where the semiconductor losses supersede the capacitor voltage ripple; especially, as all the above control methods are able to keep the capacitor voltage ripples well within the tolerable limits. Additionally, the use of arm energy balancing in the practical MMC (where the cell capacitances may have large tolerances) may lead to substantial voltage difference between upper and lower arms of the same phase leg; thus, leading to appearance of even harmonic voltages and currents in the baseband. This paper presents a new cell arrangement that can reduce MMC semiconductor losses beyond that of the HB-MMC; eliminate the need for the protective thyristor used in HB-MMC to deviate part of the fault current from the freewheeling diodes of the main switches which bypass the cell capacitors when the converter is blocked during dc fault; and facilitate continued operation of the MMC during internal cell failure, without the need for mechanical bypass switches. The viability of the proposed cell is demonstrated using simulations and experimentations. In these demonstrations, a switching model of the MMC with 16 cells and 32 capacitors per arm is used to illustrate device (modulation, capacitor voltage balancing and semiconductor losses) and system aspects (pole-to-pole dc short circuit, unbalanced operation and internal fault management), and two prototypes of the singlephase MMC with HB and proposed cells for loss and performance comparison. It has been shown that the proposed MMC is promising as it has lower semiconductor loss compared to HB-MMC, and its unique cell structure enables dc short circuit survival over an extended period, without the need for protective thyristor as in the HB-MMC.  Apart from the aforesaid attributes, an MMC that uses the cells in Figure 3(a) has the same number of cell capacitors, switching devices in conduction path and loss distribution as in conventional HB cells in Figure 3(c), including the efficiency. Figure 3 presents an alternative sub-module arrangement that inherits all the attributes of the cell arrangement in Figure 3(a), and offers new set of features such as reduced semiconductors losses and improved utilization of semiconductor switches. Table 1 summarises the switch states of the sub-modules in Figure 3(b). Voltage level 'V c ' offers redundant switch states that can be exploited to balance capacitors C 1 and C 2 within each sub-module at the cell level, without increasing capacitor voltage ripple.
Notice that a zero voltage level, which is used to bypass the cell capacitors C 1 and C 2 could be achieved by turning on switches S 2 , S 3 , S 5 and S 6 simultaneously. This leads to distribution of the arm current 'i a ' between two parallel paths, S 2 S 3 and S 5 S 6 , each carries half of the arm current (½i a ); thus, leading to reduced conduction loss per cell compared to conventional HB cell.
Additionally, the protective thyristor 'T' being used to deviate part of the dc fault current from the freewheeling diodes of the switches S 2 and S 3 in conventional HB cell in Figure 3(c) or in the cell arrangement in Figure 3(a) are no longer required, because the freewheeling diodes of switches S 2 S 3 and S 5 S 6 will be sufficient to handle dc fault current over extended period of time. Also, the mechanical bypass switch in each HB cell in Figure 3(c) could be eliminated as the semiconductor switches S 2 and S 3 could be used to bypass the damaged cell.
When the cell arrangement in Figure 3(b) is used in a generic MMC in Figure 3(d), its modulation and control remain the same as in HB-MMC case. Therefore for phase 'a', the upper and lower arm modulation functions are: Amplitude modulation and cell capacitor voltage balancing of the MMC that uses the submodule in Figure 3(b) can be performed using one of the following methods:  Table 1: Summary of switch states of the sub-module arrangement in Figure 3(b); switches S1 to S6 represent composite switching devices that comprise of IGBT plus anti-parallel diodes and , and  stand for states of charge of the cell capacitors (unchanged, charge and discharge) for different arm current polarity A) Method I: this method is summarised as follows: 1) All cell capacitor voltages are indexed as V cij , where 'i' identifies the location of individual cell in each arm ( i  and it varies from 1 to n ); and 'j' points to the location of individual capacitor within each submodule ( j  and it varies from 1 to 2).
2) Marquardt's capacitor voltage balancing method that sorts the capacitor voltages of each arm in ascending or descending order could be applied to select the number of cell capacitors to be switched in and out the power path, taking into account the voltage level to be synthesized in each sampling period, cell capacitor voltage magnitudes and arm current polarities. Insertion functions that determine the number of submodules to be inserted and bypassed from the upper and lower arms for phase 'a' are: 3) Since the precise locations of the submodule capacitors to be inserted into power path and that to be bypassed are known from step 2), the mapping summarized in Table 1 can be directly used to generate the gating signals for individual switches S ik , where 'k' varies from 1 to 6 and k  .

B) Method II:
This method is summarised as follows: 3) The status vector  that was created in step 2) will be used to determine the number of capacitors to be inserted into power path  Table 1, the gating signals of individual switches are generated and voltage across the cell capacitors C 1k and C 2k of each k th submodule are balanced locally, taking into account arm current polarity.

4) Using information provided by vector σ and mapping in
Notice that in method I, the cell capacitor voltage balancing in step 2) is performed in similar manner as that in conventional HB-MMC, while in the method II, the cell capacitor voltage balancing is performed at cell level, which is simpler and faster. A flow chart that depicts implementation steps of method II is provided in the appendix, Figure 14.  and (e) shows that phase 'a' common-mode current is practically dc with its parasitic component (2 nd harmonic current) is successfully suppressed to nearly zero. Figure 4 (g) shows the common and differential-mode ac powers the upper and lower arm cell capacitors of phase 'a' exchange with the dc and ac sides. Observe that the common and differential-mode ac powers oscillate at 2 nd harmonic and fundamental frequencies and adhere to the following analytical expressions: which are identical to that of the HB-MMC; where, p ac1 =v a1 i a1 and p ac2 =v a2 i a2 , and P and Q are the average active and reactive powers the converter exchanges with the ac side or load. The absence of dc components in both ac power components confirm that the upper and lower arm cell capacitors exchange zero average active power with the dc and dc sides; thus, natural balancing of the cell capacitor voltages could be ensured with simple cell rotation as suggested originally [35]. The differential and common-mode energies displayed in Figure 4 (h) and (i) indicate that the converter being studied has constant average commonmode energy and zero average differential-mode energy; and the latter indicates that the energy balance between the upper and lower arm cell capacitors is ensured (vertical balancing). These common and differential mode energies are described analytically as follows: The upper and lower arm cell capacitors energies are: Where, From (3) and (4), common and differential mode energies are: Observe that equations (5) and (6) agree with the simulation waveforms for the common and differential-mode energies presented in Figure 4 (h) and (i). Equations (5) and (6) indicate that the common and differential mode energies could be manipulated through the 2 nd and 1 st harmonic currents. Whilst Figure 4 (d) shows the common-mode currents of the three phase legs have the same magnitude, which indicates that the horizontal balancing or even distribution of dc link current between the three phases is ensured.
The voltage waveforms across the switching devices S 1 , S 2 and S 3 and S 5 in Figure 4 (j), (k) and (l) indicate that the switching devices of the MMC which employs the proposed cell operate at reduced average switching frequency as in HB-MMC. Since the composite switch S 2 S 3 in Figure 3(b) is exposed to multilevel voltage waveform as in Figure 4  Recall that I d =⅓I dc (I dc is the dc link current) and I 0 =½I m (where, I m represent peak of the output phase current). From Figure 3 (b) and Figure 5(a) and Table 2, currents in the IGBTs and diodes of the switches being used to bypass the cell capacitors in each phase leg are () Using these definitions of i Tb (t) and i Db (t), the equivalent average and root mean square currents in the IGBTs and diodes of the switches being employed to bypass 'n' cell capacitors are approximated by: Using expressions (7) to (10), the on-state losses of the switches S 2 S 3 and S 5 S 6 being used to bypass 'n' cell capacitors from each phase leg are computed using: where, R Don and R Ton , and V Do and V To are on-state resistances and threshold voltages of the diode and IGBT that form a single composite switch S 2 S 3 and S 5 S 6 . However, insertion of 'n' cell capacitors using switch states that generate 'V c ' and '2V c ' from each arm insert 'n' switches of mixed combinations (diodes and IGBTs) into conduction path, see Table 2 and Figure 3(b). This introduces some imperfections, which are handled in this paper using average on-state resistance and threshold voltage of the IGBT and diode (R on =½(R Don +R Ton ) and V T =½(V Do +V To )), and their equivalent average and root mean square currents are approximated by: Using expressions (7) to (10), the on-state losses of the switches S 2 S 3 and S 5 S 6 being used to bypass 'n' cell capacitors from each phase leg are computed using: Notice that equations (7) to (15) could be applied to HB-MMC (see cell in Figure 3(c)) should '½'in (11) and (12) is omitted.  To demonstrate the improved efficiency of the MMC that uses proposed cell in Figure 3(b) compared to that uses HB cell, the on-state losses of MMCs that employ these two cells are presented in Table 3. The on-state loss estimated in Table 3 are computed, assuming the following rated parameters: 1052MVA converter with 640kV (±320kV) dc link voltage; 352kV line-toline ac voltage, which is corresponding to 0.9 modulation index; and considering three operating points shown in Table 3. In this study, 4.5kV IGBT(T1800GB45A) from Westcode is assumed, with a voltage stress per switch of 2.0kV. Analytical and simulation on-state losses summarized in Table 3 indicate that the MMC with the proposed cell arrangement has lower on-state loss than the conventional HB-MMC. It has been found that presented analytical method overestimates the on-state losses of both converters being compared by a maximum of 6% with respect to that being computed using detailed simulation (on-state loss of individual device is calculated using measured currents and then added together), considering three operating points in Table 3. are average turn-on and turn-off energy losses over one fundamental cycle, and f on and f off are switching frequencies. With freewheeling diodes recovery losses being neglected, Table 4 and Table 5 show that the switching losses and total semiconductor losses of the MMC with the proposed cell arrangement are lower than that of the HB-MMC. The results in Table 3, Table 4 and Table 5 all indicate that the MMC that uses the proposed cell arrangement outperforms the HB-MMC from semiconductor loss point of view. Please refer to [36,37] for more detailed method for semiconductor loss calculations, where diode recovery losses are taken into account. With power loss cost assumed to be 3M€/MW per year [38], the savings over project lifetime of 30 years between the two converters are displayed in Table 5.

IV. REDUCED SCALE EXPERIMENTATIONS
This section uses reduced scale experimentations to compare the performance of the MMC that employs the presented cell in Figure 3(b) against that uses the conventional HB cell. Figure 6 shows schematic diagrams and prototypes of both converters, with test rig parameters listed in Table 6. Modulation and capacitor voltage balancing are programmed on low-cost 32-bit Cypress microcontroller (CY8CKIT-050 PSoC® 5LP). Due to the reduced number of cells per arm (4 cells), pulse width modulation with 2.4kHz carrier frequency is used (carriers are arranged in phase disposition fashion). Experimental waveforms presented in Figure   7 (a) to (e) and Figure 8  These results also agree with experimental results summarised in Table 7 and Figure 8   (a) Pre-filter output voltage (5ms/div and 40V/div) (a) Pre-filter output voltage (5ms/div and 40V/div) (b) Phase voltage spectrum (b) Phase voltage spectrum (c) Output phase current(5ms/div and 5A/div) c) Output phase current(5ms/div and 5A/div) (d) Upper and lower arm current and output phase or load current (5ms/div and 5A/div).  Figure 9 shows the test system that represents 84MVA converter terminal of symmetrical monopole HVDC link, with ±40kV dc link voltage, connected to 66kV ac grid through 80MVA, 40kV/66kV ac transformer with 20% per unit reactance. The proposed MMC is modelled using a detailed switch model, with 16 cells (32 cell capacitors) per arm, arm inductance L d =10mH, and each cell capacitance is rated at 2.5kV and 8mF. DC cable parameters are given in Figure 9, with ac side high impedance grounding adopted as suggested in [39,40] to define the insulation level for the dc side. In this example, the MMC being studied is equipped with active and reactive power controllers, a fundamental current controller in d-q frame, circulating current controller and cell capacitor voltage balancing (overall control system is similar to that in [41]). At startup, the converter station is commanded to inject active power of 64MW into ac grid, at bus B at unity power factor. A permanent pole-to-pole dc short circuit fault is applied in the middle of the dc line at time t=0.5s, and active power injection into B is reduced to zero immediately, with gating signals to converter switches inhibited after 50µs from fault initiation.  Figure 10(d) shows current waveforms in the switches S 2 and S 6 , which are exploited for generation of zero voltage level at each cell during normal operation, and to share the current stress when the converter is blocked during pole-to-pole dc short circuit fault. In this illustration, the on-state resistance for the diodes of the composite switches S 2 and S 3 are deliberately set to be 90% of that of the S 5 and S 6 to mimic the potential mismatch in the typical semiconductor switches may be employed (see data sheet of IGBT T1800GB45A for on-state resistance).
Observe that the arm current is shared well between the parallel paths provided by the diodes of the switches S 2 and S 3 , and S 5 and S 6 . This clearly supports the case for elimination of the thyristors being used in HB cell in Figure 3(c) to relieve diodes of the main switches that bypass the cell capacitors from excessive overcurrent during dc short circuit fault. Figure 10(e) presents current waveform in the switch S 1 , which is in series with capacitors C 1 of each cell. Observe that the current in this switch has dropped to zero when the converter is blocked as expected (no discharge of the cell capacitor). Figure 10 2) Information of fault location is used to identify the affected and unaffected cell capacitors; hence, status vector (Ψ) for the affected arm that contains zeros and ones is generated, with zeros and ones pointing to the locations of the unaffected and affected capacitors within each cell in the faulty arm. For an MMC with n cell capacitors, and M faulty cell, status vector is Ψi=δ(i-k); where, δ is Dirac function and it is defined as δ(i-k)=0 ik  and δ(i-k)=1 ik  ; i =1 to n; and k is natural number stands for location of faulty cell.
3) Each affected capacitor (C i ) is omitted from the group of capacitors to be selected to synthesize different output voltages by setting its corresponding capacitor voltage V ci =2×max(V c ) for i arm ≥0 and V ci =0.5×min(V c ) for i arm < 0; where, V c ={V c1 ,V c2 ,…….V cn }.
Based on the outlined points, the gating signals for the switching devices of the faulty cells are modified. Figure 12 shows simulation waveforms for the fault scenarios described above. These waveforms indicate that the MMC which uses the proposed cell can manage its internal cell faults safely as that in the HB-MMC case. Simulation waveforms for the hypothetical case presented in Figure 12 (time for fault detection and needed for activation of the fault management are assumed to be infinitesimal) show no evidence of transients in the arm or output phase currents when partial bypass of cells 6 and 7 are initiated at t=0.25s, and complete bypass of the cell 4 is activated at t=0.5s, see Figure   12

C) Unbalanced operation
This section examines the performance of the MMC that adopts the proposed cell during unbalanced operation initiated by deliberate connection of 1.2Ω and 0.8Ω resistors between phase b and ground and c and ground at t=0.8s, and results for this case are displayed in Figure 13. Figure 13(a) and (b) display three-phase voltages measured at bus B and currents at converter terminal (measured at the low-voltage side of the interfacing transformer). Observe that although three-phase voltages at the grid side are severely unbalanced, the currents the converter injects exhibit limited unbalance as expected. The plots for upper and lower arm currents in Figure 13 (c) and (d), common-mode currents in Figure 13(e) and dc link currents in Figure 13(f) show no penetration of 2 nd order harmonic into the dc positive and negative dc link currents, with the 2 nd harmonic currents in converter arms suppressed. These are achieved with the conventional decoupled controller of the positive sequence currents in frame, and resonance based controller for 2 nd harmonic suppression in converter arms. The plot for the common-mode currents in Figure 13 (e) indicates that each converter phase contributes unequal dc currents to the dc link current (I dc ), and this in contrary to some of the control methods in the literature that advocate dc current balancing, which may lead to overcurrent of the phases that experience larger voltage depressions. The above discussions indicate that the MMC with the proposed cell could operate satisfactory under unbalanced condition as HB-MMC.  Table 8 summaries the main similarities and differences between the HB and the proposed cell in Figure 3 (c) and (b), assuming that both cells use semiconductor switches with similar voltage and current ratings, and two HB cells are equivalent to one of the proposed cell in Figure 3 (b). Table 8 shows that both cells being compared have similar semiconductor areas, with the proposed cell in Figure 3 (b) offering the best overall performance and utilization of these semiconductor devices. Table 8: Global comparison between the proposed cell in Figure 3(b) and equivalent half-bridge cells in Figure 3(c) Semiconductor loss low Lower than HB cell, see Table 5 Number of isolated dc-dc converter for gate drives 2 (per two cells) 1 (per cell) Dynamic response good The same as HB-MMC VII. CONCLUSIONS This paper presents an alternative cell arrangement that uses its zero voltage level to reduce semiconductor losses of modular type converters to less than that of the HB-MMC, should the two additional IGBTs incorporated into the propose cell (instead of two protective thyristors in equivalent HB cells) are utilized as described above. The same IGBTs being used to reduce semiconductor losses could be exploited to bypass the faulty cells during internal converter faults; thus, making the use of mechanical bypass switch redundant. The presented simulation and experimental results show that the MMC which uses the proposed cell inherit all the attributes of the HB-MMC, including internal fault management; scalability to high-voltage applications; and transient performance during ac and dc network faults. The viability of the proposed cell arrangement at device and system levels is confirmed using simulations.

VIII. APPENDIX
This appendix presents a flow chart that summarises implementation of the method II, which is employed to perform capacitor voltage balancing in this paper.