A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations

Chen, Haochang and Zhang, Yongliang and Li, David Day-Uei (2017) A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations. IEEE Transactions on Instrumentation and Measurement, 66 (7). 1912 - 1921. ISSN 0018-9456 (https://doi.org/10.1109/TIM.2017.2663498)

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Abstract

This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28nm Field Programmable Gate Array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the non-uniformity originated from carry chains, and use a multi-phase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [-0.38, 0.87] LSB (the least significant bit: 10.5 ps) with σDNL = 0.20 LSB, and the integral nonlinearity (INL) is within [-1.23, 1.02] LSB with σ INL = 0.50 LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNLpk-pk (peak-to-peak DNL) and INLpk-pk (peak-to-peak INL) can be reduced to 0.08LSB with σDNL = 0.01LSB and 0.13 LSB with σINL = 0.02LSB respectively.

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