Gleskova, Helena and Wagner, Sigurd (2001) DC-gate-bias stressing of a-Si:H TFTs fabricated at 150ºC on polyimide foil. IEEE Transactions on Electron Devices, 48 (8). pp. 1667-1671. ISSN 0018-9383Full text not available in this repository. (Request a copy from the Strathclyde author)
We investigated the electrical stability of a-Si:H TFTs with mobilities of ∼0.7 cm 2/Vs fabricated on 51 μm thick polyimide foil at 150°C. Positive gate voltage V g ranging from 20 to 80 V was used in the bias stress experiments conducted at room temperature. The bias stressing caused an increase in threshold voltage and subthreshold slope, and minor decrease in mobility. Annealing in forming gas substantially improved the stability of the TFTs. The threshold voltage shift exhibited a power law time dependence with the exponent γ depending on the gate bais V g. For V g = 20 V, γ = 0.45, while for V g = 80 V, γ = 0.27. The threshold voltage shift also exhibited a power law dependence on V g with the exponent β depending slightly on stress duration. β = 2.1 for t = 100 sec and 1.7 for t - 5000 s. These values fall into the range experimentally observed for a-Si:H TFTs fabricated at the standard temperatures of 250-350°C.
|Keywords:||amorphous semiconductors, elemental semiconductors, hydrogen plasma, thin film transistors, electrical engineering, Electrical engineering. Electronics Nuclear engineering, Electronic, Optical and Magnetic Materials, Electrical and Electronic Engineering|
|Subjects:||Technology > Electrical engineering. Electronics Nuclear engineering|
|Department:||Faculty of Engineering > Electronic and Electrical Engineering|
|Depositing user:||Strathprints Administrator|
|Date Deposited:||18 Jan 2008|
|Last modified:||06 Jan 2017 04:36|