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Rapid prototyping - area efficient FIR filters for high speed FPGA implementation

MacPherson, K.N. and Stewart, R.W. (2006) Rapid prototyping - area efficient FIR filters for high speed FPGA implementation. IEE Proceedings Vision Image and Signal Processing, 153 (6). pp. 711-720. ISSN 1350-245X

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Abstract

A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware. Fully pipelined, full-parallel transposed-form FIR filters with multiplier block were generated using the new and previous algorithms, implemented on an FPGA target and the results compared. Previous research in this field has concentrated on minimising multiplier block adder cost but the results presented here demonstrate that this optimisation goal does not minimise FPGA hardware. Minimising multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm.

Item type: Article
ID code: 4669
Keywords: FIR filters, impulse response filters, array hardware, arithmetic technique, power systems, electrical engineering, Electrical engineering. Electronics Nuclear engineering
Subjects: Technology > Electrical engineering. Electronics Nuclear engineering
Department: Faculty of Engineering > Electronic and Electrical Engineering
Unknown Department
Related URLs:
    Depositing user: Strathprints Administrator
    Date Deposited: 08 Nov 2007
    Last modified: 16 Jul 2013 20:40
    URI: http://strathprints.strath.ac.uk/id/eprint/4669

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