Picture of wind turbine against blue sky

Open Access research with a real impact...

The Strathprints institutional repository is a digital archive of University of Strathclyde research outputs.

The Energy Systems Research Unit (ESRU) within Strathclyde's Department of Mechanical and Aerospace Engineering is producing Open Access research that can help society deploy and optimise renewable energy systems, such as wind turbine technology.

Explore wind turbine research in Strathprints

Explore all of Strathclyde's Open Access research content

Transporting multiple classes of traffic over a generic routing device - an investigation into the performance of the rapidio interconnect architecture

McKenny, M. and Dines, J. and Harle, D.A. (2003) Transporting multiple classes of traffic over a generic routing device - an investigation into the performance of the rapidio interconnect architecture. In: ICON 2003. IEEE, New York, pp. 39-44. ISBN 0780377885

Full text not available in this repository. (Request a copy from the Strathclyde author)

Abstract

RapidIO(TM) is a pseudo-serial, source-synchronous, point-to-point interconnect which enables reliable, high-speed intra-system communication. The RapidIO physical layer utilises Low-Voltage Differential Signaling (LVDS) pairs that interconnect RapidIO link partners belonging to end-points or central switch fabrics. The following is an investigation into the performance of the RapidIO architecture when deployed as the interconnection between the components of a generic switch device. A discrete event simulation model of such a system has been developed enabling various compositions of traffic to be offered to the device. Extensive simulations have enabled a quantitative analysis of various performance metrics that indicate how the device deals with various classes of traffic under saturating and non-saturating aggregate traffic loads. The results therefore provide an insight into the general performance capabilities of the RapidIO architecture as a transport protocol as well as outlining some specific issues regarding implementing RapidIO to interconnect components of a generic switch device