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The Strathprints institutional repository is a digital archive of University of Strathclyde's Open Access research outputs. Strathprints provides access to thousands of Open Access research papers by University of Strathclyde researchers, including by researchers from the Department of Computer & Information Sciences involved in mathematically structured programming, similarity and metric search, computer security, software systems, combinatronics and digital health.

The Department also includes the iSchool Research Group, which performs leading research into socio-technical phenomena and topics such as information retrieval and information seeking behaviour.

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Transporting multiple classes of traffic over a generic routing device - an investigation into the performance of the rapidio interconnect architecture

McKenny, M. and Dines, J. and Harle, D.A. (2003) Transporting multiple classes of traffic over a generic routing device - an investigation into the performance of the rapidio interconnect architecture. In: ICON 2003. IEEE, New York, pp. 39-44. ISBN 0780377885

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Abstract

RapidIO(TM) is a pseudo-serial, source-synchronous, point-to-point interconnect which enables reliable, high-speed intra-system communication. The RapidIO physical layer utilises Low-Voltage Differential Signaling (LVDS) pairs that interconnect RapidIO link partners belonging to end-points or central switch fabrics. The following is an investigation into the performance of the RapidIO architecture when deployed as the interconnection between the components of a generic switch device. A discrete event simulation model of such a system has been developed enabling various compositions of traffic to be offered to the device. Extensive simulations have enabled a quantitative analysis of various performance metrics that indicate how the device deals with various classes of traffic under saturating and non-saturating aggregate traffic loads. The results therefore provide an insight into the general performance capabilities of the RapidIO architecture as a transport protocol as well as outlining some specific issues regarding implementing RapidIO to interconnect components of a generic switch device