Picture of smart phone in human hand

World leading smartphone and mobile technology research at Strathclyde...

The Strathprints institutional repository is a digital archive of University of Strathclyde's Open Access research outputs. Strathprints provides access to thousands of Open Access research papers by University of Strathclyde researchers, including by Strathclyde researchers from the Department of Computer & Information Sciences involved in researching exciting new applications for mobile and smartphone technology. But the transformative application of mobile technologies is also the focus of research within disciplines as diverse as Electronic & Electrical Engineering, Marketing, Human Resource Management and Biomedical Enginering, among others.

Explore Strathclyde's Open Access research on smartphone technology now...

An implementation of a gigabit Ethernet AES encryption engine for application processing in SDR

Denning, D. and Irvine, J. and Harold, N. and Dunn, P. and Devlin, M. (2004) An implementation of a gigabit Ethernet AES encryption engine for application processing in SDR. In: 60th IEEE Vehicular Technology Conference, 2004-09-26 - 2004-09-29.

Full text not available in this repository. (Request a copy from the Strathclyde author)

Abstract

In this paper, we present a Gigabit Ethernet AES (Advanced Encription Standard) Encription Engine. One of the main push factors in software-defined radio(SDR) is the use of programinable devices such as field programmable gate arrays (FPGAs) or digital a signal processors (DSPs). Including such devices in SDR base station systems allows for reconfiguration and upgrade of the communication system and the application processing. Due to the increased concerns regarding secure information, we have implemented an AES encryption engine for data processing in a SDR system using one of the latest FPGAs available. The engine is capable of simultaneously processing 2 input and 2 output data streams of 1 Gigabit each. As the system has been developed on an inchistrial scalable architecture, a further 3 FPGA daughter cards can be added to the board for further application processing, and each board could be one of many.