Denning, D. and Irvine, J. and Devlin, M. (2004) Compact iterative FPGA camellia algorithm implementations. In: 3rd International Conference on Field-Programmable Technology, 2004-12-06 - 2004-12-08, Brisbane.
Full text not available in this repository. (Request a copy from the Strathclyde author)Official URL: http://dx.doi.org/10.1109/FPT.2004.1393287
Abstract
In this paper we present various iterative Camellia encryption algorithm implementations. The algorithm uses a 128-bit key, which keeps the algorithm as small as possible. The purpose for this implementation is for low-cost or area-restricted implementations suitable for embedded or mobile applications. We discuss the design and implementation considerations for a feedback architecture and achieve a throughput of 426Mbits/sec without key scheduling and 388Mbit/sec with key scheduling.
| Item type: | Conference or Workshop Item (Paper) |
|---|---|
| ID code: | 39124 |
| Keywords: | compact, iterative fpga, camellia algorithm, implementations, cryptography , throughput , scheduling, public key , portfolios, iterative algorithms, field programmable gate arrays , feedback, electronic government , digital signatures, Electrical engineering. Electronics Nuclear engineering |
| Subjects: | Technology > Electrical engineering. Electronics Nuclear engineering |
| Department: | Faculty of Engineering > Electronic and Electrical Engineering |
| Related URLs: | |
| Depositing user: | Pure Administrator |
| Date Deposited: | 12 Apr 2012 14:18 |
| Last modified: | 04 Oct 2012 17:14 |
| URI: | http://strathprints.strath.ac.uk/id/eprint/39124 |
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