Picture of wind turbine against blue sky

Open Access research with a real impact...

The Strathprints institutional repository is a digital archive of University of Strathclyde research outputs.

The Energy Systems Research Unit (ESRU) within Strathclyde's Department of Mechanical and Aerospace Engineering is producing Open Access research that can help society deploy and optimise renewable energy systems, such as wind turbine technology.

Explore wind turbine research in Strathprints

Explore all of Strathclyde's Open Access research content

Hardware co-simulation in system generator of the AES-128 encryption algorithm

Denning, D.J. and Devlin, M. and Irvine, J. (2004) Hardware co-simulation in system generator of the AES-128 encryption algorithm. In: ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004-02-22 - 2004-02-23.

Full text not available in this repository. (Request a copy from the Strathclyde author)

Abstract

We discuss the use of System Generator to hardware co-simulate in the FPGA versions of the AES-128 encryption algorithm. We show that the FPGA co-simulation of the AES can be achieved over 3 different bus types (TCP/IP, board-level TCP/IP, and PCI). One of the FPGA co-simulations is over 3 times faster running over a TCP/IP network distance off approximately 600 kilometres, than running a normal Simulink simulation on the host PC. Another hardware co-simulation time increases in the region of 4000% running over the PCI bus attached to the host PC. By having this FPGA co-simulation option, some of the IP cores in an FPGA system can be co-simulated, there by freeing up processing power on the host-PC for further developments in a system.