Picture of athlete cycling

Open Access research with a real impact on health...

The Strathprints institutional repository is a digital archive of University of Strathclyde's Open Access research outputs. Strathprints provides access to thousands of Open Access research papers by Strathclyde researchers, including by researchers from the Physical Activity for Health Group based within the School of Psychological Sciences & Health. Research here seeks to better understand how and why physical activity improves health, gain a better understanding of the amount, intensity, and type of physical activity needed for health benefits, and evaluate the effect of interventions to promote physical activity.

Explore open research content by Physical Activity for Health...

Hardware co-simulation in system generator of the AES-128 encryption algorithm

Denning, D.J. and Devlin, M. and Irvine, J. (2004) Hardware co-simulation in system generator of the AES-128 encryption algorithm. In: ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004-02-22 - 2004-02-23.

Full text not available in this repository. Request a copy from the Strathclyde author

Abstract

We discuss the use of System Generator to hardware co-simulate in the FPGA versions of the AES-128 encryption algorithm. We show that the FPGA co-simulation of the AES can be achieved over 3 different bus types (TCP/IP, board-level TCP/IP, and PCI). One of the FPGA co-simulations is over 3 times faster running over a TCP/IP network distance off approximately 600 kilometres, than running a normal Simulink simulation on the host PC. Another hardware co-simulation time increases in the region of 4000% running over the PCI bus attached to the host PC. By having this FPGA co-simulation option, some of the IP cores in an FPGA system can be co-simulated, there by freeing up processing power on the host-PC for further developments in a system.