Robertson, I. and Irvine, J. and Lysaght, P. and Robinson, D. (2002) Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series. In: ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays, 2002-02-24 - 2002-02-26, Monterey, California.
10.1.1.19.2146_1_.pdf - Draft Version
Download (496kB) | Preview
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized.
|Item type:||Conference or Workshop Item (Paper)|
|Keywords:||timing verification, dynamically reconfigurable logic, Xilinx Virtex, FPGA series, Electrical engineering. Electronics Nuclear engineering|
|Subjects:||Technology > Electrical engineering. Electronics Nuclear engineering|
|Department:||Faculty of Engineering > Electronic and Electrical Engineering|
|Depositing user:||Pure Administrator|
|Date Deposited:||21 Mar 2012 16:37|
|Last modified:||23 Jul 2015 14:05|
Actions (login required)