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Low FPGA area multiplier blocks for full parallel FIR filters

Macpherson, Kenneth N. and Stewart, Robert (2004) Low FPGA area multiplier blocks for full parallel FIR filters. In: Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology. IEEE, 247 - 254. ISBN 0-7803-8651-5

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Abstract

A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.

Item type: Book Section
ID code: 38057
Keywords: arithmetic, field programmable gate arrays, finite impulse response filter , FIR filters, distributed arithmetic technique, Electrical engineering. Electronics Nuclear engineering
Subjects: Technology > Electrical engineering. Electronics Nuclear engineering
Department: Faculty of Engineering > Electronic and Electrical Engineering
Related URLs:
    Depositing user: Pure Administrator
    Date Deposited: 01 Mar 2012 14:15
    Last modified: 09 May 2014 05:24
    URI: http://strathprints.strath.ac.uk/id/eprint/38057

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