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Evaluation of a network on chip architecture based on the clockwork routed manhattan street network using hardware emulation

Oommen, K. and Harle, D.A. (2005) Evaluation of a network on chip architecture based on the clockwork routed manhattan street network using hardware emulation. In: 48th Midwest Symposium on Circuits and Systems, 2005-08-07 - 2005-08-10.

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Abstract

Trends in integrated circuit design indicate a shift in focus from computation to communication. Interconnect issues within devices now come to the fore as the dedicated wire and shared-bus architectures look increasingly ill-equipped to cope with such complexity. This paper proposes a scalable network on chip architecture based on the Manhattan street network (MSN) using clockwork (CW) routing scheme. The proposed solution is self routing and allows for the implementation of routing functionality in hardware, eliminating the need for custom routing tables at each node. In this study, the characteristics of the proposed architecture are evaluated based upon the first full hardware implementation of a functional MSN-CW. Due to the deterministic nature of the routing mechanism, upper bounds on network delay can be established. This makes the architectures particularly suited to applications involving realtime constraints

Item type: Conference or Workshop Item (Paper)
ID code: 37981
Keywords: clocks , wire , upper bound, routing, network-on-a-chip , integrated circuit synthesis, hardware , emulation, computer architecture, integrated circuit interconnections, Electrical engineering. Electronics Nuclear engineering
Subjects: Technology > Electrical engineering. Electronics Nuclear engineering
Department: Faculty of Engineering > Electronic and Electrical Engineering
Related URLs:
    Depositing user: Pure Administrator
    Date Deposited: 28 Feb 2012 15:02
    Last modified: 17 Jul 2013 15:21
    URI: http://strathprints.strath.ac.uk/id/eprint/37981

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