Strathprints Home | Open Access | Browse | Search | User area | Copyright | Help | Library Home | SUPrimo

IP core for hardware RAID 6 acceleration

Gilroy, M.P. and Irvine, J. and Riddell, Gideon (2006) IP core for hardware RAID 6 acceleration. In: IP Based SOC Design Conference and Exhibition, 2006-12-06 - 2006-12-07, Grenoble.

Full text not available in this repository. (Request a copy from the Strathclyde author)

Abstract

As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware

Item type: Conference or Workshop Item (Paper)
ID code: 37373
Keywords: IP core, hardware, RAID 6, acceleration, Electrical engineering. Electronics Nuclear engineering
Subjects: Technology > Electrical engineering. Electronics Nuclear engineering
Department: Faculty of Engineering > Electronic and Electrical Engineering
Related URLs:
Depositing user: Pure Administrator
Date Deposited: 03 Feb 2012 16:45
Last modified: 17 Jul 2013 15:34
URI: http://strathprints.strath.ac.uk/id/eprint/37373

Actions (login required)

View Item