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IP core for hardware RAID 6 acceleration

Gilroy, M.P. and Irvine, J. and Riddell, Gideon (2006) IP core for hardware RAID 6 acceleration. In: IP Based SOC Design Conference and Exhibition, 2006-12-06 - 2006-12-07.

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Abstract

As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware