Robinson, I. and Irvine, J. (2004) A design flow for partially reconfigurable hardware. ACM Transactions in Embedded Computing Systems, 3 (2). pp. 257-283. ISSN 1539-9087
Full text not available in this repository. (Request a copy from the Strathclyde author)Abstract
This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing), synthesis, automatic placement and routing, partial configuration generation and control of partially reconfigurable designs. Collectively these tools constitute the dynamic circuit switching CAD framework. A partially reconfigurable Viterbi decoder design is presented to demonstrate the design flow and illustrate possible power consumption reductions and performance improvements through the exploitation of partial reconfiguration.
| Item type: | Article |
|---|---|
| ID code: | 3486 |
| Keywords: | FPGA, Viterbi decoder, configuration control, power estimation, electrical systems, control systems, computer aided engineering, Electrical engineering. Electronics Nuclear engineering, Electronic computers. Computer science |
| Subjects: | Technology > Electrical engineering. Electronics Nuclear engineering Science > Mathematics > Electronic computers. Computer science |
| Department: | Faculty of Engineering > Electronic and Electrical Engineering |
| Related URLs: | |
| Depositing user: | Strathprints Administrator |
| Date Deposited: | 21 Jun 2007 |
| Last modified: | 04 Oct 2012 11:50 |
| URI: | http://strathprints.strath.ac.uk/id/eprint/3486 |
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