Picture of aircraft jet engine

Strathclyde research that powers aerospace engineering...

The Strathprints institutional repository is a digital archive of University of Strathclyde's Open Access research outputs. Strathprints provides access to thousands of Open Access research papers by University of Strathclyde researchers, including by Strathclyde researchers involved in aerospace engineering and from the Advanced Space Concepts Laboratory - but also other internationally significant research from within the Department of Mechanical & Aerospace Engineering. Discover why Strathclyde is powering international aerospace research...

Strathprints also exposes world leading research from the Faculties of Science, Engineering, Humanities & Social Sciences, and from the Strathclyde Business School.

Discover more...

Improved functional simulation of dynamically reconfigurable logic

Robertson, I. and Irvine, J. and Lysaght, P. and Robinson, D. (2002) Improved functional simulation of dynamically reconfigurable logic. In: Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. Lecture Notes in Computer Science, 2438 . Springer, pp. 152-161. ISBN 978-3-540-44108-3

Full text not available in this repository. (Request a copy from the Strathclyde author)

Abstract

Several techniques to simulate dynamically reconfigurable logic (DRL) have been published during the last decade. These methods each have their own strengths and weaknesses, and perform well when used under particular circumstances. This paper introduces a revised version of dynamic circuit switching (DCS), a DRL simulation technique reported previously, which improves the accuracy of the simulation models and extends the range of situations to which they can be applied. The internal state of dynamic tasks that contain memory elements can change when they are reconfigured. Modelling this presents a further simulation requirement. The paper indicates how this can be achieved by including the ideas behind another simulation technique, clock morphing, in the methodology. Finally, the run-time overheads introduced by the technique are analysed.