Strathprints logo
Strathprints Home | Open Access | Browse | Search | User area | Copyright | Help | Library Home | SUPrimo

A key agile 17.4 Gbit/sec Camellia implementation

Denning, Daniel and Irvine, James and Devlin, Malachy (2004) A key agile 17.4 Gbit/sec Camellia implementation. In: Field-Programmable Logic and Applications (FPL) 14th International Conference Proceedings. Lecture Notes in Computer Science, 3203 . Springer-Verlag, Berlin-Heidelberg, pp. 546-554. ISBN 3-540-22989-2

Full text not available in this repository. (Request a copy from the Strathclyde author)

Abstract

In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II FPGA device.

Item type: Book Section
ID code: 22302
Notes: Paper presented at the 14th international conference on Field Programmable Logic and Applications (FPL), Belgium, 2004.
Keywords: key agile Camellia implementation, NESSIE, cryptographic algorithms, secret keys, Camellia algorithm, Electrical engineering. Electronics Nuclear engineering
Subjects: Technology > Electrical engineering. Electronics Nuclear engineering
Department: Faculty of Engineering > Electronic and Electrical Engineering
Related URLs:
Depositing user: Strathprints Administrator
Date Deposited: 17 Sep 2010 14:03
Last modified: 12 Mar 2012 11:14
URI: http://strathprints.strath.ac.uk/id/eprint/22302

Actions (login required)

View Item