A key agile 17.4 Gbit/sec Camellia implementation

Denning, Daniel and Irvine, James and Devlin, Malachy; Becker, Jurgen and Platzner, Marco and Vernalde, Serge, eds. (2004) A key agile 17.4 Gbit/sec Camellia implementation. In: Field-Programmable Logic and Applications (FPL) 14th International Conference Proceedings. Lecture Notes in Computer Science, 3203 . Springer-Verlag, Berlin-Heidelberg, pp. 546-554. ISBN 3-540-22989-2

Abstract

In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II FPGA device.

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• Item metadata

  Item type:	Book Section
  ID code:	22302
  Dates:	Date Event 2004 Published
  Notes:	Paper presented at the 14th international conference on Field Programmable Logic and Applications (FPL), Belgium, 2004.
  Subjects:	Technology > Electrical engineering. Electronics Nuclear engineering
  Department:	Faculty of Engineering > Electronic and Electrical Engineering
  Depositing user:	Strathprints Administrator
  Date deposited:	17 Sep 2010 13:03
  Last modified:	08 Apr 2024 12:36
  Related URLs:	Related item
  URI:	https://strathprints.strath.ac.uk/id/eprint/22302