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The effect of pipelining feedback loops in high speed DSP systems

Alexander, S.W. and Stewart, R.W. (2005) The effect of pipelining feedback loops in high speed DSP systems. In: UNSPECIFIED.

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Abstract

Many of today’s Electronic Design Automation (EDA) tools include Intellectual Property (IP) cores that are fully pipelined to increase data throughput. Using these cores to implement data paths that do not involve feedback can result in fast, efficient designs. However, if they are used within a feedback loop this is not always the case. This paper examines the effects that using pipelined cores in feedback loops can have on a design. By considering two designs that implement a Givens rotation using feedback, which is used in QR decomposition [1], it is shown that, even though a pipelined design can be clocked faster, its data throughput is less than a non-pipelined design. Also, the non-pipelined design is shown to be smaller and consumes less power. Finally, a suggestion for a more efficient use of pipelining in feedback loops is presented, based on channel interleaving [2].

Item type: Conference or Workshop Item (Paper)
ID code: 11456
Notes: This paper appears in: Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on ISSN: 1520-6149 ; Print ISBN: 0-7803-8874-7
Keywords: pipelining, feedback loops, DSP systems, Electrical engineering. Electronics Nuclear engineering
Subjects: Technology > Electrical engineering. Electronics Nuclear engineering
Department: Faculty of Engineering > Electronic and Electrical Engineering
Related URLs:
Depositing user: Strathprints Administrator
Date Deposited: 25 Jul 2011 17:03
Last modified: 17 Jul 2013 15:19
URI: http://strathprints.strath.ac.uk/id/eprint/11456

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